1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a burn-in test circuit and method of a semiconductor memory device which is capable of simultaneously applying a stress voltage to a plurality of word lines. The burn-in test circuit and method of the present invention is operative in both the wafer and package states of production, enabling the rapid detection and removal of defective devices in both phases.
2. Description of the Related Art
Once semiconductor memory devices are produced, a screening operation is performed to detect and remove defective devices to ensure the overall quality of the devices. In one such screening operation, a burn-in test is executed, which can involve both field acceleration and temperature acceleration. In a burn-in test commonly called a stress test, the device is operated in a state wherein the voltage and temperature are set much higher than the normal operating voltage and temperature of the device. Moreover, a stress voltage higher than that which frequently causes initial failure during normal operation is applied to the device during a short time period. As a result, a device in which a defect may not otherwise exist until the device's initial operation is instead detected beforehand and removed from production. This results in final products with improved reliability.
One of the burn-in circuits known in the conventional art is a wafer burn-in (hereinafter referred to as WBI) circuit such as that disclosed on pages 639-642 of "1993 IEEE" by Tohru Furuyama of Japan. This WBI circuit is illustrated in FIG. 1, which shows a DRAM (dynamic random access memory) wafer structure, wherein the DRAM contains a plurality of memory cells each having an access transistor 2 and a storage capacitor 4 which are disposed between a word line driver 6 and a sense amplifier 8. Sources of NMOS transistors 10 are respectively connected to a final terminal of each word line W/L1-W/Ln, and drains thereof are connected to an extra pad Vg. Gates of NMOS transistors 10 are connected to another extra pad Vstress and one plate of the storage capacitor 4 within the DRAM cell is connected to another extra pad Vpl. In the structure described above, the burn-in test is performed by applying the stress voltage to each word line via the extra pads. The burn-in stress time for a single word line is obtained by dividing the overall burn-in time by 4K, in the case of a 4K refresh product. When the above WBI is adopted in the DRAM, since the stress voltage is simultaneously applied to all of the selected word lines W/L, there exists an advantage that the overall burn-in time can be reduced.
However, since extra pads Vg, Vstress, and Vpl are not bonded when the device is packaged, the burn-in test is limited to being performed only when the device is in the wafer state. Accordingly, the burn-in test can not be performed when the device is in the package state. Furthermore, with this burn-in test, the need to prevent the burn-in test from being executed by a user after the product is manufactured is not necessary, since the device can only be tested in the wafer state. Due to these problems, the fabricating process must be restrained due to the need to perform the burn-in test when the device is in the wafer state and, furthermore, performance of the burn-in test during a shorter span of time has not been possible.